Aufgabe:
Define digital/system architecture as per system requirement and understand/derive spec, design partitioning and implement blocks in SV RTL accordingly Interact with Analog engineers; derive/define specification and analog/digital boundary protocol Verify the design implementation at block level using block level test bench or top-level test bench Synthesis, scan insertion and ATPG generation. Define/write assertion in the design. CDC, RDC, logic check by Questa/spyglass, LINT. Handle project design independently Interact with P&R engineers for physical implementation Post Silicon debug and check functionality in lab Technical communication with customer and/or marketing; presentation in design reviews, etc. Defining / tracking / working to ensure schedule adherenceQualifikation:
Master Degree in Electrical Engineering or similar; experience in Digital IC Design ASIC development, with proficiency in design of blocks and system level design Expertise in Architecture development and RTL coding. Should have experience in handling multiple clock domain Strong knowledge of serial protocols like I2C, I3C, SPI etc. and their implementation Experience in verification, synthesis, scan insertion, ATPG and timing analysis, early design analysis, CDC. (for example: irun, Xcelium, DC, Genus, Primetime, Tempus, Tetramax, spyglass, Questa). Proficiency in scripting using perl, shell, Tcl, python, GNU make etc. Low level programming in C Experience in interacting with physical design team to complete timing closer and successful implementation Experience/Knowledge of mixed signal blocks like ADC, DAC and other analog blocks like integrator, power management blocks from digital perspective is a plus Experience in DSP and implementation of different Digital Filters like CIC, decimation is a plus. Experience in data representation in different numbering format and working with algorithm is a plus English knowledge is required, German is a plusWeitere Angebote in den Bereichen:
